Scope
and Motivation
MEDEA
aims to continue the high level of interest of the previous editions held with
PACT Conference since 2000.
Dealing with memory performance is always of the utmost importance for
building and deploying efficient computer systems. For this reason, there is
always great interest in evaluating and proposing processor, multiprocessor,
CMP, multi-core and system architectures dealing with the "memory
wall" problem, as well as with the emerging limited bandwidth at the
on-chip/off-chip interface. At the same time, a modular high-level design is
becoming more and more attracting in order to reduce design costs.
In this scenario, design solutions and their corresponding performance
are shaped by the combined pressure of a) technological opportunities and
limitations, b) features and organization of system architecture and c)
critical requirements of specific application domains. Evaluating and
controlling the effects on the memory subsystem (e.g. caches or local memories,
interconnections, on-chip/off-chip interfaces, coherence, consistency and
communication management) of any architectural proposal is extremely important
both from the performance (e.g. bandwidth, latency, predictability) and power (e.g.
static, dynamic, management) points of view.
In particular, the emerging trend of single-chip multi-core solutions,
will push towards new design principles for memory hierarchy and
interconnection networks, especially when the design is aimed to build systems
with a high number of cores, which aim to scale performance and power
efficiency in a variety of application domains.
From a slightly different point of view, the mutual interaction between
the application behavior and the system on which it executes, is responsible of
the figures of merit of the memory subsystem and, therefore, pushes towards
specific solutions. In addition, it can suggest specific compile/link time
tunings for adapting the application to the features of the target
architecture.
In the overall picture, power consumption requirements are increasingly
important cross-cutting issues and raise specific challenges.
Typical architectural choices of interest include, but are not limited
to, single processors, chip and board multiprocessors, SoC, traditional and
tiled/clustered architectures, multithreaded or VLIW architectures with
emphasis on single-chip design, massive parallelism designs, heterogeneous
architectures, architectures equipped with application-domain accelerators as
well as endowed with reconfigurable modules and GPGPUs. Application domains
encompass embedded (e.g. multimedia, mobile, automotive, automation, medical),
commercial (e.g. Web, DB, multimedia), scientific and networking applications,
security, etc. Network on chip infrastructures, emerging photonic network and
transactional memory may suggest new solutions and issues.
MEDEA Workshop wants to continue to be a forum for academic and
industrial people to meet, discuss and exchange their ideas, experience and
solutions in the design and evaluation of architectures for embedded,
commercial and general/special purpose systems taking into account memory
issues, both directly and indirectly.
Proceedings of the Workshop will be published under
ACM ISBN, and appear also in the ACM Digital Library. We are trying to host a
selection of papers in a Computer Architecture Journal (in progress).
The format of the workshop includes the presentation of selected papers
and discussion after each presentation.
-
Memory
hierarchy design, analysis and tuning for embedded, general and special purpose
systems
-
On-chip
Multicore and System On Chip architectures,
development tools and applications
o
Issues
in memory hierarchy design of scalable single chip systems
o
Memory
hierarchy issues for heterogeneous, accelerator-based systems and GPGPUs
o
Solutions
for embedded, DSP, commercial, scientific and technical workloads
o
Inter-Chip
and Intra-Chip bandwidth issues and solutions
o
Inter-Chip
and Intra-Chip memory latency tolerant and reduction techniques
-
Coherence,
consistency and communication management
-
Exploitation
of application parallelism (e.g.: ILP, TLP, DLP) related to memory issues
-
Compile/link
time optimization techniques
-
Network
On Chip and Photonic Networks
-
Low-Power/Wire
Delay design of memory hierarchies
-
Transactional
Memory
-
Academic/industrial
experience in high performance, embedded systems and memory design
Pierfrancesco
Foglia, foglia@iet.unipi.it
Roberto
Giorgi, http://www.dii.unisi.it/~giorgi/,
Università di Siena, Italy
Cosimo
Antonio Prete, prete@iet.unipi.it, Università
di Pisa, Italy
Manuel
E. Acacio Sánchez,
Universidad de Murcia, Murcia, Spain
Erik
Altman, IBM T.J. Watson Research Center, NY, USA
Alessio
Bechini, Universita' di
Pisa, Pisa, Italy
Davide
Bertozzi, Universita' di Ferrara, Ferrara, Italy
Matthias.
Blumrich, IBM T.J. Watson Research Center, NY, USA
John
Cavazos, University of Delaware, Newark, Delaware, USA
Derek
Chiou, University of Texas at Austin, TX, USA
Marcelo
Cintra, University of Edinburgh, Edinburgh, UK
Jose'
Flich, Universidad Politecnica
de Valencia, Valencia, Spain
Bjoern Franke, University of
Edinburgh, Edinburgh, UK
Paul
Gratz, Texas A&M University, College Station, TX,
USA
Jaehyuk Huh, Korea Adv.Inst.Sci.&Techn.,
Daejeon, Korea
Koji
Inoue, Kyushu University, Fukuoka, Japan
Timothy
Jones, University of Edinburgh, Edinburgh, UK
David
Kaeli, Dana Research Center, NEU, Boston, MA, USA
Krishna
Kavi, University of North Texas, Denton, Texas, USA
Changkyu Kim, Intel Corporation, Santa Clara, CA, USA
Hiroaki
Kobayashi, Tohoku University, Sendai, Japan
David
M. Koppelman, Lousiana
State University, Baton Rouge, LA, USA
Avi
Mendelson, Microsoft R&D
Center, Israel
Aleksandar Milenkovic,
University of Alabama, Huntsville, AL, USA
Afrin Naz,
Drake University, Des Moines, IA, USA
Yang
Ni, Intel Corporation, Santa Clara, CA, USA
Julio
Sahuquillo, DISCA, Universitat
Politecnica de Valencia, Spain
Toshinori Sato, Fukuoka
University, Japan
Andre'
Seznec, IRISA, Rennes Cedex, France
Cristina
Silvano, Politecnico di Milano, Milano, Italy
Per
Stenstrom, Chalmers University of Technology,
Gothenburg, Sweden
Theo
Ungerer, University of Augsburg, Augsburg, Germany
Mateo
Valero, Universitat Politecnica de Catalunya, Barcelona, Spain
Ayal Zaks, IBM R&D Labs,
Haifa, Israel
Wei
Zhang, Southern Illinois University, Carbondale, IL, USA
The papers should be 6-8 pages in length. The
abstracts and papers should be submitted in PDF format by email to Pierfrancesco Foglia and Sandro Bartolini. Paper
should be written in standard ACM
SIG Proceedings Template.
To speed-up the reviewing process, we encourage also
submission of abstract by June 28, 2009.
|
|
|
|
June, 28 2009 |
Abstract Submission
(not mandatory) |
|
July, 5 2009 |
Paper Submission
Deadline |
|
August, 7 2009 |
Acceptance Notification |
|
August, 25 2009 |
Final Papers
Due |
|
September, 13 2009 |
Workshop
will start |
Attendees are requested to go to the hosting PACT'09 conference to
perform the registration
to Medea-2009 and make room reservations in the conference hotels. We suggest
that you make your room reservation in advance and register before the advance
registration deadline to benefit from combined PACT'09/Medea'09 registration
fees.
·
Performance Tuning and Analysis of Future Vector Processors Based on the
Roofline Model
Yoshiei Sato, Ryuichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi
·
Achieving High Memory Performance from Heterogeneous Architectures with
the SARC Programming Model
Roger Ferrer, Vicenç Beltran, Marc González, Xavier Martorell,
Eduard Ayguadé
·
Temperature Reduction Analysis in Sentry Tag Cache Systems
Mostafa Farahani and Amirali Baniasadi
·
Performance Balancing: Software-based On-chip Memory Management for
Effective CMP Executions
Naoto Fukumoto, Kenichi Imazato, Koji
Inoue, Kazuaki Murakami
·
Memory Management Thread for Heap Allocation Intensive Sequential
Applications
Devesh Tiwari, Sanghoon
Lee, James Tuck, Yan Solihin
·
PSMalloc: Content Based Memory Management for MPI Applications
Susmit Biswas, Diana Franklin, Timothy Sherwood,
Frederic T. Chong, Bronis R. de Supinski,
Martin Schulz
8-30: Welcome message
8:35 – 10:00 Session I: Performance and power issues in
memory systems
Performance Tuning and
Analysis of Future Vector Processors Based on the Roofline Model
Yoshiei Sato1, Ryuichi Nagaoka1, Akihiro
Musa2, Ryusuke Egawa1, Hiroyuki Takizawa1,
Koki Okabe1, Hiroaki
Kobayashi1
1Tohoku
University, Japan
2NEC
Corporation, Japan
Achieving High Memory
Performance from Heterogeneous Architectures with the SARC Programming Model
Roger Ferrer, Vicenç Beltran, Marc González, Xavier Martorell,
Eduard Ayguadé
Barcelona Supercomputing
Center, Universitat Politècnica
de Catalunya, Barcelona, Spain
Temperature Reduction
Analysis in Sentry Tag Cache Systems
Mostafa Farahani1,2 and Amirali Baniasadi1,3
1School of Computer Science, Inst. for Research in
Fundamental Sciences (IPM), Tehran, Iran
2Electrical and Computer Engineering Department, Shahid Beheshti University,
Tehran, Iran
3Electrical and Computer Engineering Dept., Univ.of Victoria, Victoria, British Columbia, Canada
10:00 – 10:30 Morning
Break
10:30 – 12:00 Session II: Memory management issues
Performance Balancing:
Software-based On-chip Memory Management for Effective CMP Executions
Naoto Fukumoto, Kenichi
Imazato, Koji Inoue, Kazuaki Murakami
Kyushu University, 744 Motooka, Nishi-ku, Fukuoka City,
Japan
Memory Management Thread
for Heap Allocation Intensive Sequential Applications
Devesh Tiwari, Sanghoon
Lee, James Tuck, Yan Solihin
Dept. of Electrical and Computer
Engineering, North Carolina State University, Raleigh, USA
PSMalloc: Content Based Memory Management for MPI
Applications
Susmit Biswas1, Diana Franklin1,
Timothy Sherwood1, Frederic T. Chong1,
Bronis R. de Supinski2, Martin Schulz2
1Department of Computer Science, University of California, Santa Barbara,
USA.
2Lawrence Livermore National Laboratory, USA.
Note: Each talk is assigned
about 30 minutes. Ideally, 22-25 minutes for the presentation and 5 minutes for
Q&A.