MEDEA-2005
aims to continue the high level of interest of the previous editions held
with PACT Conference since 2000.
Due to
the ever-increasing gap between CPU and memory speed, there is a great
interest in evaluating and proposing processor, multiprocessor and system
architectures dealing with the "memory wall" and the wire-delay problems.
One of the most interesting approaches is based on decoupling resources,
both on-chip and off-chip. In addition, a modular high-level design is
becoming more and more important in order to reduce design costs.
In this
scenario, system design issues, with particular emphasis on memory subsystem,
should be addressed taking into account the combined effect of the system
architecture and the particular application domain. In fact, the interaction
between the behavior of the application and the system on which it executes
stresses the memory subsystem and pushes towards specific solutions.
Typical
architectural choices include single processor vs. multiprocessor/multicore
solutions, traditional vs. clustered architectures, superscalar, multithreaded
or VLIW architectures with emphasis on single chip design. Application
domains encompass commercial (Web, DB, and multimedia), embedded (personal,
mobile, automotive, automation and medical), networking applications, etc.
MEDEA-2005
Workshop wants to be a forum for academic and industrial people to meet,
discuss and exchange their ideas, experience and solutions in the design
and evaluation of architectures for embedded, commercial and general purpose
systems aimed to address memory performance issues.
As in
the previous editions, accepted papers, in an extended form if needed,
will appear on the March 2006 special issue of ACM SigArch
Computer Architecture News ). The format
of the workshop includes presentations of selected papers and discussion
after each presentation. Selected papers may be considered for pubblication
on the Journal of Embedded Computing (ISSN 1740-4460).
-On-chip
Multiprocessors and System On Chip
oarchitectures,
development tools and applications
o
Memory Hierarchy Issues for Heterogeneous Systems
o
solutions for embedded, DSP, commercial, scientific and technical workloads
o
Inter-Chip and Intra-Chip memory latency tolerant and reduction techniques
o
Code optimization techniques
-Academic/industrial
experience in
University
of Siena, Italy
Pierfrancesco
Foglia, foglia@iet.unipi.it
University
of Pisa, Italy
Roberto
Giorgi, giorgi@dii.unisi.it
Cosimo
Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy
Alessio Bechini, mailto:a.bechini@iet.unipi.it
University of Pisa, Italy
Mats Brorsson, Mats.Brorsson@imit.kth.se
Royal Inst. of Techn. Stockholm, Sweden
Ali Hurson, hurson@cse.psu.edu
Penn. State University, PA, USA
David Kaeli, kaeli@ece.neu.edu
Northeastern University, MA, USA
Krishna Kavi, kavi@cs.unt.edu
University of North Texas, TX, USA
Stephen Keckler, skeckler@cs.utexas.edu
University of Texas at Austin, TX, USA
Hiroaki Kobayashi, koba@isc.tohoku.ac.jp
Tohoku University, Sendai, Japan
David M. Koppelman, koppel@ece.lsu.edu
Louisiana State Univ., Baton Rouge, LA, USA
Sally McKee, sam@csl.cornell.edu
Cornell University, NY, USA
Enrico Martinelli, enrico@dii.unisi.it
University of Siena, Italy
Alexander Milencovich, milenka@eng.uah.edu
University of Alabama, Huntsville, AL
Veljko Milutinovic, vm@ubbg.etf.ac.yu
University of Belgrade, Serbia, YU
Sanjay Patel, sjp@crhc.uiuc.edu
University of Illinois, Il, USA
Toshinori Sato, toshinori.sato@computer.org
Kyushu Institute of Technology, Iizuka, Japan
Naohiko Shimizu, pshimizu@fa2.so-net.ne.jp
Tokai University, Hiratsuka-city, Japan
Alan J. Smith, smith@cs.berkeley.edu
Univ. of California, Berkeley, CA
Mateo Valero, mateo@ac.upc.es
Universidad Politecnica de Catalunya, Spain
Theo Ungerer, ungerer@informatik.uni-augsburg.de,
University of Augsburg, DE, EU
Stamatis Vassiliadis, mailto:S.Vassiliadis@et.tudelft.nl
T.U. Delft, The Netherlands.
Wei Zhang, zhang@engr.siu.edu.
Southern Illinois University, Carbondale, IL.
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Abstract Submission
(not mandatory)
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Paper Submission
Deadline
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Acceptance Notification
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Final Papers Due
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Workshop
will start in
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Dusty Caches for Reference Counting Garbage Collection
A. Friedman, P. Krishnamurthy, R. Chamberlain, R. K. Cytron, J. E. Fritts
Data Trace cache: an application specific cache architecture
S. Ramaswamy, J. Sreeram, S. Yalamanchili, K. V. Palem
Making a case for split data caches for embedded applications
A. Naz, K. Kavi, M. Rezaei, W. Li
Exploiting the Replication Cache to Improve Cache Read Bandwidth Cost-Effectively
B. Allu, W. Zhang, M. Kandala
An Efficient Synchronization Technique for Multiprocessor Systems
M. Monchiero, G. Palermo, C. Silvano, O. Villa
Hiding message delivery and reducing memory access latency by providing
direct-to-cache transfer during receive operations in a message passing environment
F. Khunjush, N. J. Dimopoulos
NPCryptBench: A Cryptographic Benchmark Suite for Network Processors
Y. Yue, C. Lin, Z. Tan
Memory Bandwidth Optimization through Stream Descriptors
A. Lopez-Lagunas, S. M. Chai
Energy-efficient instruction scheduling exploiting memory access slack
A. Chiyonobu, T. Sato
Analysis of Embedded Video Coder Systems: a System Level Approach
A. Bardine, A. Bechini, P. Foglia, C.A. Prete
Dusty Caches for Reference Counting Garbage Collection
A. Friedman, P. Krishnamurthy, R. Chamberlain, R. K. Cytron, J. E. Fritts, Washington University, St. Louis, Missouri.
Data Trace cache: an application specific cache architecture
S. Ramaswamy, J. Sreeram, S. Yalamanchili, K. V. Palem, Georgia Institute of Technology, Atlanta, Georgia.
Making a case for split data caches for embedded applications
A. Naz, K. Kavi, M. Rezaei, W. Li, The University of North Texas, Denton, Texas.
Exploiting the Replication Cache to Improve Cache Read Bandwidth Cost-Effectively
B. Allu, W. Zhang, M. Kandala, Southern Illinois University, Carbondale, Illinois.
15:00 - 15:30 Break
An Efficient Synchronization Technique for Multiprocessor Systems
M. Monchiero, G. Palermo, C. Silvano, O. Villa, Politecnico di Milano, Italy.
Hiding message delivery and reducing memory access latency by providing direct-to-cache transfer during receive operations in a message passing environment
F. Khunjush, N. J. Dimopoulos, University of Victoria, Victoria, Canada.
NPCryptBench: A Cryptographic Benchmark Suite for Network Processors
Y. Yue, C. Lin, Tsinghua University, China, Z. Tan, University of California, Berkeley, California
Memory Bandwidth Optimization through Stream Descriptors
A. Lopez-Lagunas, ITESM Campus Toluca, Tocula, Mexico, S. M. Chai, ESPS-COE, Motorola Labs.
Energy-efficient instruction scheduling exploiting memory access slack
A. Chiyonobu, T. Sato, Kyushu Institute of Technology, Japan
Analysis of Embedded Video Coder Systems: a System Level Approach
A. Bardine, A. Bechini, P. Foglia, C.A. Prete, University of Pisa, Pisa, Italy