Papers

 
• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, Way-Adaptable D-Nuca Caches. International of High Performance Systems Architecture, ISSN 1751-6528, to appear.

• Y.N. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, X. Martorell, (Editors), High Performance Embedded Architectures and Compilers, 5th International Conference, HIPEAC2010, Pisa, Italy, 25-27 January 2010. Proceedings. Lecture Notes in Computer Science, Vol. 5952, isbn: 978-3-642-11514-1, Springer Berlin, January 2010.

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, Analysis of Performance dependencies in  NUCA-based CMP systems.  21st International Symposium on Computer Architecture and High Performance Computing (IEEE SBAC-PAD 2009), October 28 - 31, 2009, Sao Paulo, Brazil, pp. 49-56, isbn: 978-0-7695-3857-0. 2009.

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, Impact of On-Chip Network Parameters on NUCA Cache Performance. IET Computers & Digital Techniques, Vol. 3, No. 5, pp. 501-512, August 2009.

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, An Evaluation of Behaviors of S-NUCA CMPs running scientific workload.  12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD09), August 27-29, Patras, Greece, pp. 26-33, ISBN 978-0-7695-3782-5,  2009.

• P. Foglia, C.A. Prete, M. Zanda,  La Comunicazione nella Pubblica Amministrazione: Un Progetto per l'Usabilità dei Siti Web. Book chapter in "Comunicazione e Processi di Formazione. Un Approccio Interdisciplinare", di D. Coppola e P. Nicolini (Editors), pp. 183-191, ISBN 9788856813234, Franco Angeli, May 2009.

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, Investigating Design Trade-Off in S-NUCA based CMP Systems.  In Proceedings of the Workshop on UNIQUE CHIPS and SYSTEMS (UCAS-5), pp. 53-60, Boston, MA, April 26, 2009.

• M. Comparetti, P. Foglia et al, A Power-Efficient Migration Mechanism for D-NUCA Caches. Design, Automation & Test in Europe 2009 (Date 2009),  pp. 598-601, 20-24 April 2009, Nice, France.  ISBN 978-3-9810801-5-5, Nice, 2009.

• P. Foglia, G. Gabrielli, F. Panicucci, M. Solinas, Reducing Sensitivity to NoC Latency in NUCA Caches. 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC'09), pp. 72-76, Paphos, Cyprus, January 25, 2009.

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, Performance Sensitivity of NUCA Caches to On-Chip Network Parameters. 20th International Symposium on Computer Architecture and High Performance Computing (IEEE SBAC-PAD 2008), October 29 - November 1 2008, Campo Grande, Brazil, pp. 167-174, ISBN 978-0-7695-3423-7, ISSN 1550-6533. 2008

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, On-Chip Networks: Impact on the Performances of NUCA caches.  11th EUROMICRO Conference on Digital System Design, September 3-5 2008, Parma, Italy, pp. 55-56, ISBN 978-3-902457-20-3. 2008.   PDF

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, P. Stenstrom, Leveraging Data Promotion for Low Power D-NUCA Caches.  11th EUROMICRO Conference on Digital System Design , September 3-5 2008, Parma, Italy, pp. 307-316. ISBN 978-0-7695-3277-6. 2008.   PDF

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, Investigating Design Trade-Off in CMP Systems.   Proceedings of the Poster Session of the 4th International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2008), L'Aquila, Italy, July 2008.

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, Facing the False Miss Problem in D-NUCA based CMP Systems.   Proceedings of the Poster Session of the 4th International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2008), L'Aquila, Italy, July 2008.

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, CMP L2 NUCA Cache Energy Consumption Model.   Proceedings of the Poster Session of the 4th International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2008), L'Aquila, Italy, July 2008.

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, Dynamic Optimization Techniques for D-NUCA Caches.   Proceedings of the Poster Session of the 4th International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2008), L'Aquila, Italy, July 2008.

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, Implementation Issues of Way Adaptable D-NUCA Caches.   Proceedings of the Poster Session of the 4th International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2008), L'Aquila, Italy, July 2008.

• A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete, NUCA caches: Analysis of Performance Sensitivity to NOC Parameters.   Proceedings of the Poster Session of the 4th International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2008), L'Aquila, Italy, July 2008.   PDF

• P. Foglia, C. A. Prete, M. Zanda, Relating GSR Signals to traditional Usability Metrics: A Case Study with an anthropomorphic Web Assistant. 2008 IEEE International Instrumentation & Measurement Technology Conference (I2MTC2008). Victoria, Canada, May 12-15, Vol. 1, pp.  1814-1819, ISSN-ISBN 1-4244-1541-1 1091-5281. 2008. PDF

• A. Bardine. P. Foglia, G. Gabrielli, C. A. Prete, P. Stenstrom, A Micro-Architectural Power-Saving Technique for D-NUCA caches.  In Proceedings of the Workshop on UNIQUE CHIPS and SYSTEMS (UCAS-4), Austin, TX, April 20, 2008. PDF

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, CMP L2 NUCA Cache Power Consumption Reduction Technique. Proceedings of IEEE Symposium on Low Power and High-Speed Chips (COOLChips XI),Yokohama, Japan, pp. 163, April 16-18 2008. PDF

• S. Bartolini, P. Foglia,  C. A. Prete, Memory Performance: Dealing with Applications, Systems and Architecture.  ACM SIGARCH Computer Architecture News , Vol. 35, Issue4, pp. 4-5 , ISSN:0163-5964, September 2007.  PDF

• A. Bardine. P. Foglia, G. Gabrielli, C. A. Prete, P. Stenstrom, Improving Power Efficiency of D-Nuca Caches.  ACM SIGARCH Computer Architecture News , Vol. 35, Issue4, pp. 53-58 , ISSN:0163-5964, September 2007. PDF

• A. Bardine. P. Foglia, G. Gabrielli, C. A. Prete, Analysis of Static and Dynamic Energy Consumption in NUCA Caches: Initial Results. Proceedings of the MEDEA 2007 Worskhop on Memory Performance: Dealing with Applications, Systems and Architecture, Brasov, Romania, 16 September 2007, pp. 113-120. ISSN 978-1-59593-807-7, ACM Press, September 2007.  PDF

• A. Bardine. P. Foglia, G. Gabrielli, C. A. Prete, Evaluating Power Consumption of  D-NUCA caches. Proceedings of the Poster Session of the 3nd International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2007), L'Aquila, Italy, July 2007. PDF

• P. Foglia, F. Panicucci, C. A. Prete, M. Solinas, Techniques for Reducing Power Consumption in CMP NUCA caches. Proceedings of the Poster Session of the 3nd International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2007), L'Aquila, Italy, July 2007. PDF

• G. Dini, P. Foglia, C. A. Prete, M. Zanda, Effects of Increasing Users' Attention on Cost in Software Download Interfaces on the Internet. 29th International Conference on Information Technology Interfaces (ITI2007). Dubrovnik, Croatia, June 25-28  2007. ISSN 1330-1012. June 2007. PDF

• P. Foglia, C. A. Prete, M. Zanda, Modelling Public Administration Portals: Requirements, Methodologies and Tools to improve the User Experience. Encyclopedia of Portal Technology and Applications,  A. Tantnall (Editor), Vol. II, Idea Group Inc.,  ISBN 978-1-59140-989-2, June 2007. PDF

• A. Naz, K. Kavi, J.H. Oh, P. Foglia, Reconfigurable Split Data Caches: A Novel Scheme for Embedded Systems. 22th ACM Symposium on Applied Computing, Seoul, Korea, Vol. 1, pp 200-208, March 2007. ISBN 1-59593-480-4. PDF

• P. Foglia, F. Giuntoli, C. A. Prete, M. Zanda, Assisting E-Government Users with Animated Talking Faces. ACM Interactions, Vol. XIV.1, pp 24-26, January-February 2007. ISSN 1072-5220.  PDF

• A. Bardine. P. Foglia, C. A. Prete, Way Adaptable D-NUCA caches, Proceedings of the Poster Session of the 2nd International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2006), L'Aquila, Italy, July 2006.

• G. Dini, P. Foglia, C. A. Prete, M. Zanda, An Analysis of User Interface Factors influencing the Acceptance of Code Download. 28th Information Technology Interfaces Conference (ITI2006). pp. 233-238, Dubrovnik, Croatia, June 2006. ISSN 1330-1012.

• S. Bartolini, P. Foglia, C.A. Prete, Embedded Processors and Systems: Architectural Issues and Solutions for Emerging Applications, Journal of Embedded Computing (JEC), Vol. 2, Issue 1, 2006,  ISSN 1740-4460.

• P. Foglia, C. A. Prete, R. Sodini, M. Solinas, An ESB Implementation for Airport Environment, WSEAS Transactions on Systems, Vol. 6, Issue 5, pp. 1436-1441, June 2006. ISSN 1109-1441.

• P. Foglia, C. A. Prete, R. Sodini, M. Solinas, An ESB Implementation for Airport Environment, 5th WSEAS International Conference on Applied Computer Science  (ACOS'06), pp. 641-646,  Hangzhou, China, April 15-18,  2006. ISSN 1790-5109.

• S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, Memory Performance: Dealing with Applications, Systems and Architecture,  ACM SIGARCH Computer Architecture News , Vol. 34, Issue1, pp. 1-2, ISSN:0163-5964, March 2006.

• A. Bardine, A. Bechini, P. Foglia, C. A. Prete, Analysis of Embedded Video Coder System: a System Level Approach, ACM SIGARCH Computer Architecture News , Vol. 34, Issue1, pp. 71-76, ISSN:0163-5964, March  2006.

• P. Foglia, D. Mangano, C. A. Prete, A Cache Design for High Performance Embedded Systems, Journal of Embedded Computing (JEC), Vol. 1, Issue 4, pp. 587-598, 2005,  ISSN 1740-4460.

• P. Foglia, D. Mangano, C. A. Prete, A NUCA Model for Embedded Systems Cache Design, IEEE 2005 Workshop on Embedded Systems for Real-Time Multimedia (ESTIMEDIA), New York Metropolitan Area, Usa, pp. 41-46, September 2005, ISBN 0-7803-9347-3.

• A. Bardine, A. Bechini, P. Foglia, C. A. Prete, Analysis of Embedded Video Coder System: a System Level Approach, Medea 2005 Workshop , St Louis, Missouri, September 2005.

• M. Zanda, C.A. Prete, P. Foglia, Easily Usable Web Sites, the path to a high conversion rate, The 2005 Networking and Electronic Commerce Research Conference (NAEC2005), Lago di Garda, Italy, pp. 217-222, ISBN: 0-9716253-6-0, September 2005.

• S. Bartolini, P. Foglia, C. A. Prete, MEDEA04 Workshop Guests Editors' Introduction,   ACM SIGARCH Computer Architecture News , Vol. 33, Issue3, pp. 1-3, ISSN:0163-5964, June 2005.

• P. Foglia, D. Mangano, C. A. Prete, Tuning D-NUCA cache, Proceedings of the Poster Session of the 1st International  Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2005), L'Aquila, Italy, July 2005.

• C.A. Prete, P. Foglia, M. Zanda, An Innovative Tool to Easily Get Usable Web Sites, International Conference on Web Information Systems and Technologies (WEBIST), INSTICC, ISBN: 972-8865-20-1 Miami, FL, pp. 373-376, May 2005.

• P. Foglia, R. Giorgi, C. A. Prete, Reducing Coherence Overhead and Boosting Performance of High-End SMP Multiprocessors Running a DSS Workload, Journal of Parallel and Distributed Computing (JPDC),  Vol. 65, N. 3, pp. 289-306, March 2005.

• S. Bartolini, P. Foglia, C. A. Prete, MEDEA Workshop Guests Editors' Introduction,   ACM SIGARCH Computer Architecture News, Vol. 32, Issue3, pp. 85-92, ISSN:0163-5964, June 2004.

• P. Foglia, R. Giorgi, C. A. Prete, A Simulation Study of Memory Performance of SMP Multiprocessors Running a TPC-W Workload,  IEE Proceedings Computers and Digital Techniques (IEE CDT Sez. E), Vol. 151, N. 2, pp. 93-109, March 2004.

• Foglia, P., Giorgi, R. and Prete, C.A. (2004), Speeding-up multiprocessors running DBMS workloads through coherence protocols, International Journal of  High Performance Computing and Networking (IJHPCN), Vol. 1,Nos. 1/2/3, pp.17--32, 2004.

• P. Foglia, R. Giorgi, C. A. Prete, Speeding-up Multiprocessors Running DSS Workloads through Coherence Protocols,  2nd Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing (SHPSEC 2003),  New Orleans, LA, September 2003.

• S. Bartolini, P. Foglia,  C. A. Prete, ''Extending SNMP Management to GSM Radio Devices",  7th  World Multiconference on Systemics, Cybernetics, and Informatics (SCI03),  Orlando, FL, July 2003.

• S. Bartolini, P. Foglia, C. A. Prete, MEDEA Workshop Guests Editors' Introduction,   ACM SIGARCH Computer Architecture News , Vol. 31, Issue1, pp. 4-6, ISSN:0163-5964, March 2003.

• A. Bechini, P. Foglia, C. A. Prete, Fine-Grain Design Space Exploration for a Cartographic SoC Multiprocessor,   ACM SIGARCH Computer Architecture News , Vol. 31, Issue1, pp. 85-92, ISSN:0163-5964, March 2003.

• A. Bechini, P. Foglia, C. A. Prete, Use of a CORBA/RMI Gateway: Characterization of Communication Overhead,   ACM Workshop on Software and Performance (WOSP02-ISTTA02), Roma, Italy, June 2002.

• P. Foglia, R. Giorgi, C. A. Prete, Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture,   Lecture Notes in Computer Science N. 2376, pp. 134-146, Web Engineering, Pisa, Italy, May 2002.

• P. Foglia, R. Giorgi, C. A. Prete, OS Effects on Memory Hierarchy of a SMP Multiprocessor Running a DBMS Workload,   Computer & e-Business Conference, L'Aquila, Italy, August 2001.

• P. Foglia, R. Giorgi, C. A. Prete, Adapting DSS Workloads through Coherence Protocols, ACM Workshop on Caching, Coherence and Consistency (WC3'01), Sorrento, Italy, June 2001.

•  P. Foglia, R. Giorgi, C. A. Prete,  Performance Analysis of Parallel Applications Running on SMP. 2001 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'2001),  Las Vegas, USA, June 2001.

• A. Bechini and P. Foglia, "Extension of Web Server Systems for E-Commerce: Incremental Crowding vs. Functional Doubling-Up".  PADDA 2001, Int'l Workshop on Performance-oriented Application Development for Distributed Architectures, Munich (Germany), Apr. 2001.

 
•  P. Foglia, An algorithm for the Classification of Coherence Related Overhead in Shared-Bus Shared-Memory Multiprocessors. IEEE TCCA Newsletter, January 2001.

• P. Foglia, R. Giorgi, C.A. Prete: Evaluating Optimizations for Multiprocessors E-Commerce Server Running TPC-W Workload. 34th IEEE Hawaii Int. Conf. on Systems,  January 2001.

• P. Foglia, R. Giorgi, C.A. Prete: Performance Analysis of Electronic Commerce Multiprocessor Servers. 33rd IEEE Hawaii Int. Conf. on Systems,   January 2000.

• P. Foglia, R. Giorgi, C.A. Prete: Process Migration Effect on Memory Performance of Multiprocessor Web Servers. Lecture Notes in Computer Science N. 1745, pp.133-142, Proceedings of 6th High Performance Computing Conference, Calcutta, Dec. 1999.

 
• P. Foglia, R. Giorgi, C.A. Prete: Analysis of Sharing Overhead in Shared Memory Multiprocessors. 31st IEEE Hawaii Int. Conf. on Systems, January 1998.

 
• R. Giorgi, P. Foglia, C.A. Prete: Bus Utilization Analysis of Multithreaded Shared-Bud Multiprocessor: Initial Results. Proceedings of 9th Int'l Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October 1997.        Postscript gzipped file

• G.Anastasi, P. Foglia, L.Lenzini: MPEG Video Traffic On a MetaRing Network: Complexity Reduction of a Worst Case Resource Allocation Model. Computer Communications (21)2 (1998) pp. 111-125. Postscript gzipped file