News:

 

 

Scope and Motivation

MEDEA aims to continue the high level of interest of the previous editions held with PACT Conference since 2000.

Due to the ever-increasing gap between CPU and memory speed, there is always great interest in evaluating and proposing processor, multiprocessor, CMP, multi-core and system architectures dealing with the "memory wall" and wire-delay problems. At the same time, a modular high-level design is becoming more and more attracting in order to reduce design costs.

In this scenario, design solutions and their corresponding performance are shaped by the combined pressure of a) technological opportunities and limitations, b) features and organization of system architecture and c) critical requirements of specific application domains. Evaluating and controlling the effects on the memory subsystem (e.g. caches, interconnection, bus, memory, coherence) of any architectural proposal is extremely important both from the performance (e.g. bandwidth, latency, predictability) and power (e.g. static, dynamic, manageability) points of view.

In particular, the emerging trend of single-chip multi-core solutions, will push towards new design principles for memory hierarchy and interconnection networks, especially when the design is aimed to build systems with a high number of cores (many-core instead of multi-core systems), which aim to scale performance and power efficiency in a variety of application domains.

From a slightly different point of view, the mutual interaction between the application behavior and the system on which it executes, is responsible of the figures of merit of the memory subsystem and, therefore, pushes towards specific solutions. In addition, it can suggest specific compile/link time tunings for adapting the application to the features of the target architecture.

In the overall picture, power consumption requirements are increasingly important cross-cutting issues and raise specific challenges.

Typical architectural choices of interest include, but are not limited to, single processors, chip and board multiprocessors, SoC, traditional and tiled/clustered architectures, multithreaded or VLIW architectures with emphasis on single-chip design, massive parallelism designs, heterogeneous architectures, architectures equipped with application-domain accelerators as well as endowed with reconfigurable modules. Application domains encompass embedded (e.g. multimedia, mobile, automotive, automation, medical), commercial (e.g. Web, DB, multimedia), scientific and networking applications, security, etc. The emerging network on chip infrastructure and transactional memory may suggest new solutions and issues.

MEDEA Workshop wants to continue to be a forum for academic and industrial people to meet, discuss and exchange their ideas, experience and solutions in the design and evaluation of architectures for embedded, commercial and general/special purpose systems taking into account memory issues, both directly and indirectly.

Proceedings of the Workshop will be published under ACM ISBN, and appear also in the ACM Digital Library. As in the previous years, a selection of papers will be considered for publication on transactions on HIPEAC (http://www.hipeac.net/journal)

 

The format of the workshop includes the presentation of selected papers and discussion after each presentation.

 

Topics of Interest:

- Memory hierarchy design, analysis, tuning for embedded, general and special purpose systems

- On-chip Multiprocessors and System On Chip architectures, development tools and applications

- Issues in memory hierarchy design of scalable single chip systems

- Memory hierarchy issues for heterogeneous and accelerator-based systems

- Solutions for embedded, DSP, commercial, scientific and technical workloads

- Inter-Chip and Intra-Chip memory latency tolerant and reduction techniques

- Cache coherence and memory models

- Exploitation of application parallelism (e.g.: ILP, TLP, DLP)

- Transactional Memory

- Compile/link time optimization techniques

- Network On Chip

- Low-Power/Wire Delay design of memory hierarchies

- Processor and System Architectures

- Academic/industrial experience in high performance, embedded systems and memory design

Organizing and Steering Committee

 

Sandro Bartolini, http://www.dii.unisi.it/~bartolini/

Università di Siena, Italy

Pierfrancesco Foglia, foglia@iet.unipi.it

Università di Pisa, Italy

Roberto Giorgi, http://www.dii.unisi.it/~giorgi/

Università di Siena, Italy

Cosimo Antonio Prete, prete@iet.unipi.it

Università di Pisa, Italy

 

Program Committee

 

Erik Altman, IBM T.J. Watson Research Center, NY, USA

Davide Bertozzi, Università di Ferrara, Ferrara, Italy

Alessio Bechini, Università di Pisa, Pisa, Italy

Matt. Blumrich, IBM T.J. Watson Research Center, NY, USA

Vincenzo Catania, Università di Catania, Catania, Italy

John Cavazos, University of Delaware, Newark, Delaware, USA

Marcelo Cintra, University of Edinburgh, Edinburgh, UK

Derek Chiou, University of Texas at Austin, TX, USA

José Flich, Universidad Politecnica de Valencia, Valencia, Spain

Bjoern Franke, University of Edinburgh, Edinburgh, UK

Koji Inoue, Kyushu University, Fukuoka, Japan

Timothy Jones, University of Edinburgh, Edinburgh, UK

David Kaeli, Northeastern University, Boston, MA, USA

Krishna Kavi, University of North Texas, Denton, Texas, USA

Stephen Keckler, University of Texas at Austin, TX, USA

Changkyu Kim, Intel Corporation, Santa Clara, CA, USA

Hiroaki Kobayashi, Tohoku University, Sendai, Japan

David M. Koppelman, Lousiana State University, Baton Rouge, LA, USA

Enrico Martinelli, Università of Siena, Siena, Italy

Mike Marty, Google, Madison, WI, USA

Avi Mendelson, Intel, Haifa, Israel

Alexander Milencovich, University of Alabama, Huntsville, AL, USA

Afrin Naz, Drake University, Des Moines, Iowa, USA

Kunle Olukotun, Stanford University, Stanford, CA, USA

Emre Ozer, ARM, Cambridge, UK

Toshinori Sato, Fukuoka University, Japan

André Seznec, IRISA, Rennes Cedex, France

Cristina Silvano, Politecnico di Milano, Milano, Italy

Theo Ungerer, University of Augsburg, Augsburg, Germany

Mateo Valero, Universitat Politecnica de Catalunya, Barcelona, Spain

Wei Zhang, Southern Illinois University, Carbondale, IL, USA

 

 

 

Information for Authors

The papers should be 6-8 pages in length. The abstracts and papers should be submitted in PDF format by email to Pierfrancesco Foglia and Sandro Bartolini. Paper should be written in standard ACM SIG Proceedings Template.

Please email submissions by August, 7th 2008. You receive an acknowledgment of your submission by the following week. Authors will be notified of acceptance or rejection by September, 21st 2008 and the final papers are due by September, 28th 2008.

To speed-up the reviewing process, we encourage also submission of abstract by July 31st, 2008. 

All submissions will be refereed, and Proceedings with ACM ISBN will be printed and distributed at the workshop (They appear in ACM DL in the following weeks).

Important Dates

 

 

July 31st, 2008

Abstract Submission (not mandatory)

August, 7th 2008

Paper Submission Deadline

September, 21st 2008

Acceptance Notification

September, 28th 2008

Final Papers Due

October, 26th 2008

Workshop will start

Registration and accommodation

Attendees are requested to go to the hosting PACT'08 conference to perform the registration to Medea-2008 and make room reservations in the conference hotels. We suggest that you make your room reservation in advance and register before the advance registration deadline to benefit from combined PACT'08/Medea'08 registration fees.

Final Program

·        Accurate System-Level Performance Modeling and Workload Characterization for Mobile Internet Devices

M. Hayenga, C. Sudanthi, M. Ghosh, P. Ramrakhyani, N. Paver.

 

·        PFetch: Software Prefetching Exploiting Temporal Predictability of Memory Access Stream

J. Marathe, F. Mueller.

 

·        A Leakage-Aware Cache Sharing Technique for Low-Power Chip Multi-processors (CMPs) with Private L2 caches

H. Kim, S. Youn, J. Kim.

 

·        Modeling of Cache Access Behavior Based on Zipf’s Law

I. Kotera, R. Egawa, H. Takizawa, H. Kobayashi.

 

·        Version Management Alternatives for Hardware Transactional Memory

M. Lupon, G. Magklis, A. Gonzalez.

 

·        WormBench – A Configurable Workload for Evaluating Transactional Memory Systems

Z. Zyulkyarov, S. Cvijic, O. Unsal, A. Cristal, E. Ayguade, T. Harris, M. Valero.

 

·        Predictable Dynamic Instruction Scratchpad for Simultaneous Multithreaded Processors

S. Metzlaff, S. Uhrig, T. Ungerer.

 

·        A Shared Cache for a Chip Multi Vector Processor

A. Musa, Y. Sato, T. Soga, K. Okabe, R. Egawa, H. Takizawa, H. Kobayashi.

 

·        Evaluation of Memory Performance on the Cell BE with the SARC Programming Model

R. Ferrer, M. Gonzalez, F. Silla, X. Martorell, E. Ayguade.

 

·        Zero Loads: Canceling Load Requests by Tracking Zero Values

M. md. Islam, P. Stenstrom.

 

·        Exploiting Multithreaded Architectures to Improve the Hash Join Operation

L. Rashid, W. M. Hassanein, M. A. Hammad.

 

 

 

Schedule

8-30 Workshop begins: welcome message

 

8:35 – 10:00 Analyzing and exploiting memory hierarchies features

 

PFetch: Software Prefetching Exploiting Temporal Predictability of Memory Access Streams

Jaydeep Marathe, Frank Mueller

North Carolina State University, Raleigh, USA

 

Modeling of Cache Access Behavior Based on Zipf’s Law

Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

Tohoku University, Sendai, Japan

 

Zero Loads: Canceling Load Requests by Tracking Zero Values

Majiful Md. Islam, Per Stenstrom

Chalmers University of Technology, Göteborg, Sweden

 

10:00 – 10:20 Morning Break

 

10:20 – 12:00 Session II: Caching in CMP and multithreaded systems

 

A Shared Cache for a Chip Multi Vector Processor

Akihiro Musa1, Yoshiei Sato1, Takashi Soga2, Koki Okabe1, Ryusuke Egawa1

Hiroyuki Takizawa1, Hiroaki Kobayashi1

1Tohoku University, Sendai, Japan

2NEC System Technologies, Osaka, Japan

 

A Leakage-Aware Cache Sharing Technique for Low-Power Chip Multiprocessors (CMPs) with Private L2 Caches

Hyunhee Kim1, Sungjun Youn2, Jihong Kim1

1Seoul National University & 2LG Electronics Corporation, Seoul, Korea

 

Predictable Dynamic Instruction Scratchpad for Simultaneous Multithreaded Processors

Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer

University of Augsburg, Augsburg, Germany

 

Exploiting Multithreaded Architectures to Improve the Hash Join Operation

Layali Rashid, Wessam M. Hassanein, Moustafa A. Hammad

University of Calgary, Calgary, Canada

 

12:00 - 13:30 Lunch

 

13:30-15:00 Session III: Workload characterization and programming model

 

Accurate System-Level Performance Modeling and Workload Characterization

for Mobile Internet Devices

Mitchell Hayenga1, Chander Sudanthi2, Mrinmoy Ghosh2, Prakash Ramrakhyani2, Nigel Paver2

1University of Wisconsin-Madison, USA

2Arm Inc.

 

WormBench - A Configurable Workload for Evaluating Transactional Memory Systems

Ferad Zyulkyarov1, Sanja Cvijic2, Osman Unsal1, Adrian Cristal1, Eduard

Ayguadé1, Tim Harris3, Mateo Valero1

1Barcelona Supercomputing Center, Barcelona, Spain

2Belgrade University, Belgrade, Serbia

3Microsoft Research, UK

 

Version Management Alternatives for Hardware Transactional Memory

Marc Lupon1, Grigorios Magklis2, Antonio González1

1Universitat Politècnica de Catalunya, Barcelona, Spain

2Intel Barcelona Research Center, Intel Labs–UPC, Barcelona, Spain

 

15:00 - 15:20 Afternoon Break

 

15:20 - 15:45 Session III: Workload characterization and

programming model (continued)

 

Evaluation of Memory Performance on the Cell BE with the SARC Programming

Model

Roger Ferrer1, Marc González1, Federico Silla2, Xavier Martorell1, Eduard

Ayguadé1

1Barcelona Supercomputing Center, Barcelona, Spain

2Universidad Politécnica de Valencia, Valencia, Spain