News:
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This year, Guri Sohi will give in Medea the
keynote:
“So what are
we going to do with multicore processors?".
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The schedule is available.
Each author has 16 minutes for presentation, plus 4 minutes for Q&A.
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Selected Papers will appear on Vol. 3, Issue N. 2 of
Transactions on HIPEAC.
MEDEA
aims to continue the high level of interest of the previous editions held with
PACT Conference since 2000.
Due to the ever-increasing gap between CPU and memory speed, there is
always great interest in evaluating and proposing processor, multiprocessor,
CMP, multi-core, SoC and system architectures dealing with the "memory
wall" and wire-delay problems. At the same time, a modular high-level
design is becoming more and more attracting in order to reduce design costs.
In this scenario, design solutions and their corresponding performance
are shaped by the combined pressure of a) technological opportunities and
limitations, b) features and organization of system architecture and c)
critical requirements of specific application domains. Evaluating and
controlling the effects on the memory subsystem (e.g. caches, interconnection,
bus, memory, coherence) of any architectural proposal is extremely important
both from the performance (e.g. bandwidth, latency, predictability) and power
(e.g. static, dynamic, manageability) points of view.
In particular, the emerging trend of single-chip multi-core solutions,
will push towards new design principles for memory hierarchy and
interconnection networks, especially when the design is aimed to build systems
with a high number of cores (many-core instead of multi-core systems), which
aim to scale performance and power efficiency in a variety of application
domains.
From a slightly different point of view, the mutual interaction between
the application behavior and the system on which it executes, is responsible of
the figures of merit of the memory subsystem and, therefore, pushes towards
specific solutions. In addition, it can suggest specific compile/link time
tunings for adapting the application to the features of the target
architecture.
In the overall picture, power consumption requirements are increasingly
important cross-cutting issues and raise specific challenges.
Typical architectural choices of interest include, but are not limited
to, single processor, chip and board multiprocessors, SoC, traditional and
tiled/clustered architectures, multithreaded or VLIW architectures with
emphasis on single-chip design, massive parallelism designs, heterogeneous
architectures, architectures equipped with application-domain accelerators as
well as endowed with reconfigurable modules. Application domains encompass
embedded (e.g. multimedia, mobile, automotive, automation, medical), commercial
(e.g. Web, DB, multimedia), networking applications, security, etc. The
emerging network on chip infrastructure may suggest new solutions and issues.
MEDEA Workshop wants to continue to be a forum for academic and
industrial people to meet, discuss and exchange their ideas, experience and
solutions in the design and evaluation of architectures for embedded,
commercial and general/special purpose systems taking into account memory
issues, both directly and indirectly.
Proceedings of the Workshop will be published under
ACM ISBN, and appear also in the ACM Digital Library. Accepted papers will be considered
for publication, in an extended version, for the March 2008 special issue of
Transactions on HIPEAC (www.hipeac.net/journal).
The format of the workshop includes the presentation of selected papers
and discussion after each presentation.
- Memory
hierarchy design, analysis, tuning for embedded, general and special purpose
systems
- On-chip
Multiprocessors and System On Chip architectures, development tools and
applications
o Issues in memory hierarchy design of scalable single chip
systems
o Memory hierarchy issues for heterogeneous and
accelerator-based systems
o Solutions for embedded, DSP, commercial, scientific and
technical workloads
o Inter-Chip and Intra-Chip memory latency tolerant and
reduction techniques
- Cache coherence and memory models
- Compile/link time optimization techniques
- Bus/Interconnection Architectures
- Network On Chip
- Low-Power/Wire Delay design of memory hierarchies
- Processor and System Architectures
- Exploitation of application parallelism (e.g.: ILP, TLP, DLP)
- Academic/industrial experience in high performance, embedded systems
and memory design
Pierfrancesco
Foglia, foglia@iet.unipi.it
University of Pisa, Italy
Roberto
Giorgi, http://www.dii.unisi.it/~giorgi/
University of Siena, Italy
Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy
Erik Altman,
Alessio
Bechini, University of Pisa, Pisa, Italy
Koen Bertels, TUDELFT,
John Cavazos,
Bjoern Franke,
Georgi Gaydadjiev, TUDELFT,
Ali Hurson,
Timothy Jones, University
of Edinburgh, Edinburgh, UK
David Kaeli, Northeastern University,
Krishna Kavy,
Stefanos Kaxiras, University of Patras,
Greece
Stephen Keckler,
Hiroaki
Kobayashi, Tohoku University, Sendai, Japan
David
M. Koppelman, Lousiana
State University, Baton Rouge, LA, USA
Enrico
Martinelli, University of Siena, Siena, Italy
Avi Mendelson, Intel,
Alexander Milencovich,
Yale Patt,
Alex Ramirez, Universitat Politecnica de Catalunya,
Toshinori Sato,
Per Stenström,
Chalmers
Theo Ungerer,
Mateo
Valero, Universitat Politecnica de Catalunya, Barcelona,
Spain
Wei
Zhang, Southern Illinois
University, Carbondale, IL, USA
The papers should be 6-8 pages in length. The abstracts and
papers should be submitted in PDF format by email to Pierfrancesco
Foglia and Sandro Bartolini.
Paper should be written in standard ACM
SIG Proceedings Template. Hard copy (postal) submissions will not be
accepted.
To speed-up the reviewing process, we encourage also submission of
abstract by
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Abstract Submission (not
mandatory) |
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Paper Submission Deadline |
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Acceptance Notification |
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Final Papers Due |
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Workshop will start |
Attendees are requested to go to the hosting
PACT'07 conference to perform the registration to Medea-2007
and make room reservations in the conference hotels. We suggest that you make
your room reservation in advance and register before the advance registration
deadline to benefit from combined PACT'07/Medea'07 registration fees.
·
Keynote: Guri Sohi, "So what are we
going to do with multicore processors?"
·
Improving the Accuracy of Snoop Filtering Using Stream
Registers
Valentina Salapura, Matthias Blumric, Alan Gara
·
Improving Disk Bandwidth-Bound Applications Through
Main Memory Compression
Vicenç Beltran, Jordi Torres,
Eduard Ayguadé
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An On-Chip Cache Design for Vector Processors
Akihiro Musa, Yoshiei
Sato, Ryusuke Egawa,
Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi
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Parallelization Schemes for Memory Optimization on the
Cell Processor: A Case Study of Image Processing Algorithm
Tarik Saidani, Stéphane Piskorski, Lionel Lacassagne, Samir Bouaziz
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A Power-Aware Shared Cache Mechanism Based on Locality
Assessment of Memory Reference for CMPs
Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
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Multithreaded Software Transactional Memory and OpenMP
Miloš Milovanović,
Roger Ferrer, Vladimir Gajinov,
Osman S. Unsal, Adrian
Cristal, Eduard Ayguadé, Mateo Valero
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Reducing leakage in power-saving capable caches for
embedded systems by using a filter cache
P. Bennati, R. Giorgi
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Building a Large Instruction Window Through ROB
Compression
Fernando Latorre, Grigorios Magklis, José González, Pedro
Chaparro, Antonio González
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Analysis of Static and Dynamic Energy Consumption in
NUCA Caches: Initial Results
A. Bardine, P. Foglia, G.
Gabrielli, C. A. Prete
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Characterization of Apache web server with Specweb2005
Ana Bosque, Pablo Ibañez,
Víctor Viñals, Per Stenström, Jose M. Llabería
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Code-Size Conscious Pipelining of Imperfectly Nested
Loops
Mohammed Fellahi,
Albert Cohen, Sid Touati
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Broadcast Filtering-Aware Task Assignment Techniques
for Low-Power MPSoCs
Chun-Mok Chung and Jihong Kim
·
Adaptive Management of Cache Block Replication for
High-Performance CMP
Tomonobu Mihara, Koji Inoue, Kazuaki Murakami
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Data Prefetching and Address
Pre-Calculation through Instruction Pre-Execution with Two-Step Physical
Register Deallocation
Akihiro Yamamoto,
Yusuke Tanaka, Hideki Ando, Toshio Shimada
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The STAPL pArray
Gabriel Tanase, Mauro
Bianco, Nancy M. Amato, Lawrence Rauchwerger
8-30 -
Workshop begins:
welcome message
8:40 – 10:00 Session I: CMP/Parallel Systems:
Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study of Image Processing AlgorithmTarik Saidani1, Stéphane Piskorski2, Lionel Lacassagne1, Samir Bouaziz1
1Institut d’Electronique Fondamentale, Orsay, France
2Laboratoire de Recherche en Informatique, Orsay, France
An On-Chip Cache Design for Vector ProcessorsAkihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi