Scope and Motivation

 

MEDEA-2006 aims to continue the high level of interest of the previous editions held with PACT Conference since 2000.

 

Due to the ever-increasing gap between CPU and memory speed, there is a never diminishing interest in evaluating and proposing processors, multiprocessors and system architectures dealing with the "memory wall" problem. Various approaches have been proposed over the years pursuing different strategies, but recently new issues have joined the scenario, posing new challenges and opportunities. In particular, power-consumption, wire-delay effects, chip multi-core (heterogeneous) architectures and reconfigurability are some of the keywords that fuel research on memory sub-system architecture. In addition, modular high-level design methodologies are becoming more and more important in order to reduce the overall system costs, especially in the embedded system domain. In this environment, system and memory design issues should be addressed taking into account the effect of the particular application domain against the system architecture: it is the interaction between the behavior of the application and the system on which it executes that stresses the memory subsystem and pushes towards specific solutions.

The MEDEA Workshop wants to be a forum for academic and industrial people to meet, discuss and exchange their ideas, experience and solutions in the designing and evaluation of architectures for embedded, commercial and general purpose systems, aimed to solve the memory wall problem, and addressing also power consumption, wire delay effects and reconfigurable solutions.

 

As in the previous editions, papers presented at the Workshop will be published, in an extended version if needed, on a special issue of ACM SigArch Computer Architecture News.

The format of the workshop includes presentations of selected papers and discussion after each presentation.

 


Topics of Interest

 

-Memory Hierarchy Design for Embedded/General Purpose Systems

-Processor and System Architectures and their impact on memory performances

-Bus/Interconnection Architectures and their impact on memory performances

-Network On Chip

-Low-Power/Wire Delay design of memory hierarchies

-Feedback-directed optimization techniques

-On-chip Multiprocessors and System On Chip

- Memory Hierarchy Issues for Heterogeneous Systems

- solutions for embedded, DSP, commercial, scientific and technical workloads

- Inter-Chip and Intra-Chip memory latency tolerant and reduction techniques

-Academic/industrial experience in the design of high performance and embedded systems

 


Organizing and Steering Committee

 

Sandro Bartolinibartolini@dii.unisi.it

University of Siena, Italy 

Pierfrancesco Foglia, foglia@iet.unipi.it

University of Pisa, Italy 

Roberto Giorgi, giorgi@dii.unisi.it

University of Siena, Italy 

Cosimo Antonio Prete, prete@iet.unipi.it

University of Pisa, Italy

 


Program Committee

 

Erik Altman, ealtman@us.ibm.com,

    IBM T.J. Watson Research Center, NY, USA

Alessio Bechini, a.bechini@iet.unipi.it,

    University of Pisa, Italy 

Mats Brorsson, matsbror@kth.se

    Royal Inst. of Techn. Stockholm, Sweden 

John Cavazos, jcavazos@inf.ed.ac.uk,

    University of Edinburgh, UK

Bjoern Franke, bfranke@inf.ed.ac.uk,

    University of Edinburgh, UK

Ali Hurson, hurson@cse.psu.edu,

    Penn. State University, PA, USA

David Kaeli, kaeli@ece.neu.edu,

    Northeastern University, MA, USA

Stefanos Kaxiras, kaxiras@ee.upatras.gr

    University of Patras, Greece

Stephen Keckler, skeckler@cs.utexas.edu,

    University of Texas at Austin, TX, USA

Hiroaki Kobayashi, koba@isc.tohoku.ac.jp,

    Tohoku University, Sendai, Japan

David M. Koppelman, koppel@ece.lsu.edu,

    Louisiana State Univ., Baton Rouge, LA, USA

Enrico Martinelli, enrico@dii.unisi.it,

    University of Siena, Italy

Avi Mendelson, avi.mendelson@intel.com,

    Intel, Israel

Alexander Milencovich, milenka@eng.uah.edu,

    University of Alabama, Huntsville, AL

Afrin Naz, kavi@cs.unt.edu ,

    University of North Texas, TX, USA

Theo Ungerer, ungerer@informatik.uni-augsburg.de,

    University of Augsburg, DE

Toshinori Sato, toshinori.sato@computer.org,

    Kyushu University, Iizuka, Japan

Naohiko Shimizu, pshimizu@fa2.so-net.ne.jp

    Tokai University, Hiratsuka-city, Japan

Alan J. Smith, smith@cs.berkeley.edu,

    Univ. of California, Berkeley, CA, USA

Per Stenström, pers@ce.chalmers.se

    Chalmers University of Technology, Sweden

Mateo Valero, mateo@ac.upc.es ,

    Universidad Politecnica de Catalunya, Spain

Stamatis Vassiliadis, S.Vassiliadis@et.tudelft.nl

    T.U. Delft, The Netherlands.

Wei Zhang, zhang@engr.siu.edu,

    Southern Illinois University, Carbondale, IL, USA

 

 


Information for Authors 

The papers should be at most 8 pages in length. The abstracts and papers should be submitted in PDF format by email to  Pierfrancesco Foglia and Sandro Bartolini

Paper should be written in standard IEEE format for conference proceedings. Hard copy (postal) submissions will not be accepted. 

Please email submissions by July 21, 2006. You receive an acknowledgment of your submission by the following week. Authors will be notified of acceptance or rejection by  August 20, 2006 and the final papers are due by September 5, 2006

To speed-up the reviewing process, we encourage also submission of abstract by July 14, 2006

All submissions will be refereed, and informal proceedings will be printed and distributed at the workshop. Accepted papers appear in a special issue of ACM SigArch Computer Architecture News. The workshop committee may invite authors to extend their papers for inclusion in the special issue.


Important Dates

 

 

July 14, 2006

Abstract Submission (not mandatory) 

July 21, 2006

Paper Submission Deadline

August 20, 2006

Acceptance Notification

September 5, 2006

Final Papers Due

September 16, 2006 

Workshop will start in Seattle


Registration and accommodation

Attendees are requested to go to the hosting PACT'06 conference to perform the registration to Medea-2006 and make room reservations in the conference hotels. We suggest that you make your room reservation in advance and register before the advance registration deadline to benefit from combined PACT'06/Medea'06 registration fees.


Final Program

Analyzing Block Locality in Morton-Order and Morton-Hybrid Matrices

K. Patrick Lorton, David S. Wise

 

Investigating Cache Energy and Latency Break-even Points in High Performance Processors

Kaveh Jokar Deris, Amirali Baniasadi

 

Evaluating Instruction Cache Vulnerability to Transient Errors

Jun Yan, W. Zhang

 

A Simple Speculative Load Control Mechanism for Energy Saving

Tanausu Ramırez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero

 

Data prefetching in a cache hierarchy with high bandwidth and capacity

Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals

 

An LRU-based Replacement Algorithm Augmented with Frequency of Access in Shared Chip-Multiprocessor Caches

Haakon Dybdahl, Per Stenstrom, Lasse Natvig

 


Schedule

13:30 - Workshop begins: Welcome Message

 

13:40 - 15:10 Session I: Investigating the cache behavior

 

Analyzing Block Locality in Morton-Order and Morton-Hybrid Matrices

K. Patrick Lorton and David S. Wise,Indiana University, Bloomington, Indiana

 

Investigating Cache Energy and Latency Break-even Points in High Performance Processors

Kaveh Jokar Deris and Amirali Baniasadi, University of Victoria, Victoria, Canada

 

Evaluating Instruction Cache Vulnerability to Transient Errors

Jun Yan, W. Zhang, Southern Illinois University, Carbondale, Illinois
 
15:10 - 15:40 Break
 

15:40 - 17:10 Session II: Specializing the cache architecture

 

A Simple Speculative Load Control Mechanism for Energy Saving

Tanausu Ramırez1, Alex Pajuelo1, Oliverio J. Santana2, Mateo Valero1,3
1 Universitat Politecnica de Catalunya, Spain.
2 Universidad de Las Palmas de Gran Canaria, Spain. 
3 Barcelona Supercomputing Center, Spain.
 

Data prefetching in a cache hierarchy with high bandwidth and capacity

Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals, Univ. de Zaragoza, Spain

 

An LRU-based Replacement Algorithm Augmented with Frequency of Access in Shared Chip-Multiprocessor Caches

Haakon Dybdahl1, Per Stenstrom2, Lasse Natvig1
1Norwegian University of Science and Technology, Trondheim, Norway
2Chalmers University of Technology, Goteborg, Sweden