Scope and Motivation

MEDEA-2004 aims to continue the high level of interest in the previous editions of MEDEA Workshops held with PACT'00, PACT'01, PACT'02 and PACT'03.

Due to the ever-increasing gap between CPU and memory speed, there is a great interest in evaluating and proposing processor, multiprocessor and system architectures dealing with the "memory wall" problem.

In this scenario, memory performance issues can be better addressed when considering system architecture and application domain in a joint manner. In fact, it is the combined effect of the applications and the system on which they are executing that stresses the memory subsystem and pushes towards specific solutions.

Typical architectural choices include single processor vs. multiprocessor solutions, single chip vs. COTS design, superscalar, multithreaded or VLIW architectures. Application domains encompass commercial (Web, DB, e-business, and multimedia), embedded (personal, mobile, automotive, automation and medical), networking applications, etc.

The MEDEA-2004 Workshop wants to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience on the design and evaluation of architectures for embedded, commercial and general purpose systems. Main topics are memory performance issues and solutions in the various application domains.

As in the previous editions, accepted papers, in an extended form if needed, will appear on the March 2005 special issue of ACM SigArch Computer Architecture News ).

The format of the workshop includes presentations of selected papers and discussion after each presentation.

 

-Memory Hierarchy Design for Embedded Systems

-Memory Hierarchy Design for Commercial/Scientific/General Purpose Applications

-Processor and System Architecture and their impact on memory performances

-Cache memory: Organization and Coherence

-Bus/Interconnection Architecture

-Low-Power design of memory hierarchies

-Operating system memory management and virtual memory systems

-On-chip Multiprocessors and System On Chip

o architectures, development tools and applications

o solutions for embedded, commercial, scientific and technical workloads

o power consumptionand performance evaluation

o optimization

-Academic/industrial experience in 

o high performance, general purpose, embedded systems and memory design

-Multithreaded applications

-Code optimization techniques

-Memory Access Decoupling

-Latency Tolerance and Reduction techniques

-Instruction and Thread Level Parallelism 

-Workload characterization 

Sandro Bartolini, bartolini@dii.unisi.it

University of Siena, Italy 

Pierfrancesco Foglia, foglia@iet.unipi.it

University of Pisa, Italy 

Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy

Information for Authors 

Paper should be written in standard IEEE format for conference proceedings. Hard copy (postal) submissions will not be accepted. 

Please email submissions by July 18, 2004. You receive an acknowledgment of your submission by the following week. Authors will be notified of acceptance or rejection by  August 14, 2004 and the final papers are due by September 1, 2004. 

To speed-up the reviewing process, we encourage also submission of abstract by July 12, 2004. 

All submissions will be refereed, and informal proceedings will be printed and distributed at the workshop. Accepted papers appear in the March 2005 special issue of ACM SigArch Computer Architecture News. The workshop committee may invite authors to extend their papers for inclusion in the special issue.

Important Dates

 

July 12, 2004	Abstract Submission (not mandatory)
July 18, 2004	Paper Submission Deadline
August 8, 2004	Acceptance Notification
September 1, 2004	Final Papers Due
September 29, 2004	Workshop and PACT will start in Antibes Juan-les-Pins

Registration and accomodation

Final Program

• Asmaa EL OUARDIGHI, Hanene BEN FRADJ, Cécile BELLEUDY, Michel AUGUIN: Energy aware memory architecture configuration

 

• Hyo-Joong Suh, Sung Woo Chun: DRACO: Optimized CC-NUMA system with Novel Dual-Link Interconnections to Reduce the Memory Latency

 

• Sami Yehia, Jean-Francois Collard, Olivier Temam: Load Squared: Adding Logic Close to Memory to Reduce the Latency of Indirect Loads with High Miss Ratios

 

• Hiroaki Kobayashi, Isao Kotera, and Hiroyuki Takizawa: Locality Analysis to Control Dynamically Way-Adaptable Caches

 

• F. Arakawa, M. Ishikawa, Y. Kondo, T. Kamei, M. Ozawa, O. Nishii, T. Hattori: SH-X: An Embedded Processor Core for Consumer Appliances

 

• Afrin Naz, Mehran Rezaei, Krishna Kavi and Philip Sweany:  Improving Data Cache Performance With Integrated Use Of Split Caches, Victim Cache And Stream Buffers

 

• Alex Pajuelo, Antonio Gonzalez and Mateo Valero: Speculative Execution for Hiding Memory Latency

 

• Javier Verdu, Jorge Garcýa, Mario Nemirovsky, Mateo Valero: The Impact of Traffic Aggregation on the Memory Performance of Networking Applications

 

Schedule

08:00 – Workshop begins: Welcome Message

 

08:05 - 10:10 Session I: Memory Latency and Caches

Load Squared: Adding Logic Close to Memory to Reduce the Latency

of Indirect Loads with High Miss Ratios

S. Yehia, O. Temam, University of Paris-Sud, France and J. F. Collard, Hewlett-Packard Laboratories. Palo Alto, CA, USA

 

Locality Analysis to Control Dynamically Way-Adaptable Caches

H. Kobayashi, I. Kotera, H. Takizawa, Tohoku University, Japan

 

Improving Data Cache Performance with Integrated Use of

Split Caches, Victim Cache and Stream Buffers

A. Naz, M. Rezaei, K. Kavi and P. Sweany, The University of North Texas, Denton, TX, USA

 

Speculative Execution for Hiding Memory Latency

A. Pajuelo, A. Gonzalez and M. Valero, Universitat Politècnica de Catalunya,Barcelona, Spain

 

The Impact of Traffic Aggregation on the Memory Performance

of Networking Applications

J. Verdu, J. Garcia, M. Valero, Universitat Politècnica de Catalunya, Barcelona, Spain and M. Nemirovsky, Tidal Networks Inc., San Jose, CA, USA

10:10 – 10:40 Break

10:40 – 11:55 Session II: System Architectures: Design and Solutions

Energy aware memory architecture configuration

A. EL OUARDIGHI, H. BEN FRADJ, C. BELLEUDY, M. AUGUIN, Laboratoire d’Informatique, signaux et Systèmes de Sophia-Antipolis, France

 

DRACO: Optimized CC-NUMA system with Novel Dual-Link

Interconnections to Reduce the Memory Latency

H. J. Suh, The Catholic University of Korea and S. W. Chung, Samsung Electronics 

 

SH-X: An Embedded Processor Core for Consumer Appliances

F. Arakawa, M. Ishikawa, Y. Kondo, M. Ozawa, Hitachi Ltd., Japan and T. Kamei, Renesas Technology Corporation, Japan and O. Nishii, T. Hattori, SuperH, Ltd., Japan

11:55 Concluding Remarks