Scope and Motivation
MEDEA-2003
aims to continue the high level of interest in the first three MEDEA Workshops
held with PACT'00, PACT'01 and PACT'02.
Due to the ever-increasing gap between CPU and memory speed,
there is a great interest in evaluating and proposing processor, multiprocessor
and system architectures dealing with the "memory wall" problem.
In this scenario, memory performance issues can be better addressed when
considering system architecture and application domain in a joint manner. In
fact, it is the combined effect of the applications and the system on which
they are executing that stresses the memory subsystem and pushes towards
specific solutions.
Typical architectural choices include single processor vs. multiprocessor
solutions, single chip vs. COTS design, superscalar, multithreaded or VLIW
architectures. Application domains encompass commercial (Web, DB, e-business,
and multimedia), embedded (personal, mobile, automotive, automation and
medical), networking applications, etc.
The
MEDEA-2003 Workshop wants to be a forum for academic and industrial people to
meet, discuss and exchange their ideas and experience on the design and
evaluation of architectures for embedded, commercial and general purpose
systems. Main topics are memory performance issues and solutions in the various
application domains.
As
in the previous editions, accepted papers, in an extended form if needed, will
appear on the March 2004 special issue of "ACM SigArch Computer
Architecture News".
The
format of the workshop includes presentations of selected papers and discussion
after each presentation.
-
Memory Hierarchy Design
for Embedded Systems
-
Memory Hierarchy Design
for Commercial/Scientific/General Purpose Applications
-
Processor and System
Architecture and their impact on memory performances
-
Cache memory: Organization and Coherence
-
Bus/Interconnection Architecture
-
Low-Power design of memory hierarchies
-
Operating system memory management and virtual memory systems
-
On-chip Multiprocessors and System On Chip
o architectures,
development tools and applications
o solutions
for embedded, commercial, scientific and technical workloads
o power
consumptionand performance evaluation
o optimization
-
Academic/industrial experience in
o high
performance, general purpose, embedded systems and memory design
-
Multithreaded applications
-
Code optimization techniques
-
Memory Access Decoupling
-
Latency Tolerance and Reduction techniques
-
Instruction and Thread Level Parallelism
-
Workload characterization
University of Siena, Italy
Pierfrancesco Foglia, foglia@iet.unipi.it
University of
Pisa, Italy
Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy
IBM T.J. Watson Research
Center, NY, USA
Fumio Arakawa, arakawa@crl.hitachi.co.jp
Central Research Laboratory, Hitachi Ltd. , Japan
Alessio Bechini, a.bechini@iet.unipi.it
University of Pisa, Italy
Ricardo Bianchini, ricardob@cs.rutgers.edu
Rutgers University, NJ, USA
Binu Mathew, mbinu@cs.utah.edu
University of Utah, Salt Lake City, USA
Mats Brorsson, Mats, Brorsson@imit.kth.se
Royal Inst. of Techn.
Stockholm, Sweden
Roberto
Giorgi, giorgi@acm.org
University of
Siena, Italy
Antonio Gonzalez, antonio@ac.upc.es
Universidad
Politecnica de Catalunya, Spain
Jose Gonzalez, pepe.gonzalez@intel.com
Intel Labs, Barcelona, Spain
Ali Hurson, hurson@cse.psu.edu
Penn. State
University, PA, USA
Liviu Iftode, iftode@cs.umd.edu
Maryland
University, NJ, USA
David Kaeli, kaeli@ece.neu.edu
Northeastern
University, MA, USA
Krishna Kavi, kavi@cs.unt.edu
University of North Texas,
TX, USA
Stephen Keckler, skeckler@cs.utexas.edu
University of Texas at
Austin, TX, USA
Avi Mendelson, mendelson@intel.com
Intel, Israel
Enrico Martinelli, enrico@dii.unisi.it
University of Siena, Italy
Aleksander Milenkovic, milenka@ece.uah.edu
Univer. of
Alabama In Huntsville, AL, USA
Veljko Milutinovic, vm@ubbg.etf.ac.yu
University of Belgrade, Serbia, YU
Sanjay Patel, sjp@crhc.uiuc.edu
Univ. of Illinois, Il, USA
Nikos Pitsianis, nikos@cs.duke.edu
Duke University, Durham, USA
Jelica Protic, jeca@sezampro.yu
University of Belgrade,
Serbia, YU
Naohiko Shimizu, pshimizu@fa2.so-net.ne.jp
Tokai University,
Hiratsuka-city, Japan
Alan J. Smith, smith@cs.berkeley.edu
Univ. of California,
Berkeley, CA, USA
Jared Stark,jared.w.stark@intel.com
Intel, USA
Jie Tao, tao@informatik.tu-muenchen.de
Technische Universität München, Germany
Theo Ungerer, ungerer@informatik.uni-augsburg.de,
University of Augsburg, DE, EU
Mateo Valero, mateo@ac.upc.es
Universidad
Politecnica de Catalunya, Spain
The papers should be at most 8
pages in length. The abstracts and papers should be submitted in either
postscript or PDF format by email to the workshop-organizing members: Pierfrancesco Foglia and Sandro Bartolini.
Paper should be written in standard IEEE format
for conference proceedings. Hard copy (postal) submissions will not be
accepted.
To
speed-up the reviewing process, we encourage also submission of abstract by June
8, 2003.
|
June 8, 2003 |
Abstract
Submission (not mandatory) |
|
June 16, 2003 |
Paper Submission
Deadline |
|
July 14, 2003 |
Acceptance
Notification |
|
September 1,
2003 |
Final Papers
Due |
|
September 27,
2003 |
Workshop and PACT will start in New Orleans, Louisiana |
Attendees
are requested to go to the hosting PACT'03 conference to perform the registration to
Medea-2003 and make room reservations in the conference hotels. We suggest that
you make your room reservation in advance and register before the advance
registration deadline to benefit from combined PACT'03/Medea'03 registration
fees.
· A Case for Resource-Conscious Out-of-order Processors, by A. Cristal, J. F. Martinez, and M. Valero
·
A Case for Shared Instruction Cache on Chip Multiprocessors
Running OLTP , by P. Kundu, M. Annavaram, and T. Diep, J. Shen
·
The MIP Project: Evolution of a Novel Supercomputer Architecture,
by N. Venkateswaran, A. Shriraman, A. Krishnan, S. Kumar, and S. Srinivas
·
Memory Performance of Public-Key cryptography Methods in Mobile
Environments, by I. Branovic, R. Giorgi, and E. Martinelli
·
Data Cache Management on Epic Architecture: Optimizing Memory
Access for Image Processing, by K. Brifault, and H-P. Charles
·
Java Object Look Aside Buffer for Embedded Applications, by N.
Shimizu, and C. Kon
·
A Leakage-Energy-Reduction Technique for High-Associativity Caches
in Embedded Systems, by A. Sakanaka, and T. Sato
·
Hibrid-SOC: A Multi-Core Architecture For Image and Video
Applications, by S. Moch, M. Berekovic, H.J. Stolberg, L. Friebe, M. B.
Kulaczewski, A. Dehnhardtl,and P. Pirsch
·
A Scalable, Clustered SMT Processor for Digital Signal Processing
, by M. Berekovic, S. Moch, and P. Pirsch
13:00 – Workshop begins: Welcome Message
13:05 - 15:00 Session I: Exploring the
Design Space
A Case for Resource-Conscious Out-of-order ProcessorsA. Cristal, J. F. Martinez, and M. Valero - Universitat Politécnica de Catalunya, J. Llosa - Cornell UniversityA Case for Shared Instruction Cache on Chip Multiprocessors Running OLTP P. Kundu, M. Annavaram, T. Diep, J. Shen - Microprocessor Research Labs, Intel Corporation The MIP Project: Evolution of a Novel Supercomputer ArchitectureN. Venkateswaran, A. Shriraman, A. Krishnan, S. Kumar, S. Srinivas - Waran Research FoundationMemory Performance of Public-Key cryptography Methods in Mobile Environments
I. Branovic, R. Giorgi, E. Martinelli - University of SienaData Cache Management on Epic Architecture: Optimizing Memory Access for Image ProcessingK. Brifault, H-P. Charles - University of Versailles
15:00 – 15:30 Break
15:30 – 17:10 Session II: Architectures and Solutions
Java Object Look Aside Buffer for Embedded ApplicationsN. Shimizu, C. Kon - Tokai University
A Leakage-Energy-Reduction Technique for High-Associativity Caches in Embedded SystemsA. Sakanaka - Panasonic Communications Co. Ltd., T. Sato - Japan Science and Technology Corporation
Hibrid-SOC: A Multi-Core Architecture For Image and Video ApplicationsS. Moch, M. Berekovic, H.J. Stolberg, L. Friebe, M. B. Kulaczewski, A. Dehnhardtl, P. Pirsch, University of HannoverA Scalable, Clustered SMT Processor for Digital Signal ProcessingM. Berekovic, S. Moch, P. Pirsch - University of Hannover
17:10
Concluding Remarks