Scope and Motivation

MEDEA-2002 aims to continue the high level of interest in the first two MEDEA Workshops held with PACT'00 and PACT'01. 

In the previous versions MEDEA (MEmory access DEcoupled Architectures) focused on Access Decoupling, Thread Level Parallelism, ILP, Latency tolerating techniques and related issues.

Currently, there is a great interest in On-Chip Multiprocessors both for general purpose and embedded systems. Moreover, there is a growing interest in the resource clusterization, multithreading, Thread and Instruction Level Parallelism, power consumption, latency reducing techniques and workload characterizations.

The MEDEA-2002 Workshop wants to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience on On-Chip Multiprocessor issues, solutions, challenges, both in the technical, general purpose and in the embedded horizon. MEDEA-2002 is seeking submissions describing ideas and experience with On Chip Multiprocessor systems and solutions from other fields applicable to them.

The format of the workshop will include presentations of selected papers and discussion after each presentation.

Accepted papers appear in a special issue of the ACM SigArch Computer Architecture News. The workshop committee may invite authors to extend their papers for inclusion in the special issue.

Topics of Interest

-         On-chip Multiprocessors (OCM)

o       architectures

o       issues

o       solutions

o       multithreading

o       cache and memory sub-systems

o       coherence protocols

o       development tools

o       applications

o       power consumption

o       solutions for embedded, commercial, scientific and technical workloads

o       performance evaluation

o       optimization

-         Academic and Industrial Experience in OCM 

o       high performance

o       general purpose

o       embedded

-         Code optimization techniques

-         Memory Access Decoupling

-         Processor Architecture

-         Latency Tolerance and Reduction techniques

-         Instruction Level and Thread Level Parallelism 

-         System on Chip

-         Workload characterization 

Organizing Committee

Sandro Bartolini, s.bartolini@iet.unipi.it

University of Pisa, Italy 

Pierfrancesco Foglia, foglia@iet.unipi.it

University of Pisa, Italy 

Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy

Program Commitee 

Fumio Arakawa, fumio.arakawa@superh.com 
SuperH Japan Ltd., Tokyo, Japan
Alessio Bechini, a.bechini@iet.unipi.it 
University of Pisa, Italy 
Ricardo Bianchini, ricardob@cs.rutgers.edu
Rutgers University, NJ, USA
Doug Burger, dburger@cs.utexas.edu
University of Texas at Austin, TX, USA
Mats Brorsson, Mats, Brorsson@imit.kth.se
Royal Institute of Technology in Stockholm, Sweden
Roberto Giorgi, giorgi@acm.org
University of Siena, Italy 
Antonio Gonzalez, antonio@ac.upc.es
Universidad Politecnica de Catalunya, Spain
Ali Hurson, hurson@cse.psu.edu
Penn. State University, PA, USA
Liviu Iftode, iftode@cs.umd.edu
Maryland University, NJ, USA
David Kaeli, kaeli@ece.neu.edu
Northeastern University, MA, USA
Krishna Kavi, kavi@cs.unt.edu
University of North Texas, TX, USA
Stephen Keckler, skeckler@cs.utexas.edu
University of Texas at Austin, TX, USA
Avi Mendelson, mendelson@intel.com
Intel, Israel
Aleksander Milenkovic, milenka@ece.uah.edu
Univer. of Alabama In Huntsville, AL, USA
Veljko Milutinovic, vm@ubbg.etf.ac.yu
University of Belgrade, Serbia, YU
Sanjay Patel, sjp@crhc.uiuc.edu
Univ. of Illinois, Il, USA
Jelica Protic, jeca@sezampro.yu
University of Belgrade, Serbia, YU 
Alan J. Smith, smith@cs.berkeley.edu
Univ. of California, Berkeley, CA, USA 
Jared Stark, jared.w.stark@intel.com
 Intel, USA
Theo Ungerer, ungerer@informatik.uni-augsburg.de
University of Augsburg, DE, EU
Mateo Valero, mateo@ac.upc.es
Universidad Politecnica de Catalunya, Spain

Information for Authors 

The papers should be at most 10 pages in length. The abstracts and papers should be submitted in either postscript or PDF format by email to the workshop-organizing members: Pierfrancesco Foglia and Sandro Bartolini. 

Paper should be written in standard IEEE format for conference proceedings. Hard copy (postal) submissions will not be accepted. 

Please email submissions by July, 10 2002. You receive an acknowledgment of your submission by the following week. Authors will be notified of acceptance or rejection by August 1, 2002 and the final papers are due by August 7, 2002. 

To speed-up the reviewing process, we encourage also submission of abstract by July, 3 2002. 

All submissions will be refereed, and informal proceedings will be printed and distributed at the workshop. Accepted papers appear in a special issue of the ACM SigArch Computer Architecture News. The workshop committee may invite authors to extend their papers for inclusion in the special issue.

Important Dates


 

July, 3 2002

Abstract Submission (not mandatory) 

July, 10 2002

Paper Submission Deadline

August, 1 2002

Acceptance Notification

September, 2 2002

Final Papers Due

September, 22 2002 

Workshop and PACT will start in Charlottesville, Virginia

Registration and accomodation

Attendees are requested to go to the hosting PACT'02 conference to perform the registration to Medea-2002 and make room reservations in the conference hotels. We strongly suggest that you make your room reservation in advance and register before the advance registration deadline to benefit from combined PACT'02/Medea'02 registration fees.

 

Final Program

 

 

Schedule:

 

14:00 - Workshop begins: Welcome Message

 

14:05 - 15:40 Session I

 

Fresh Breeze: A Multiprocessor Chip Architecture Guided by Modular Programming Principles

Jack B. Dennis - MIT Laboratory for Computer Science

 

Realizing High IPC Through a Scalable Memory-Latency Tolerant Multipath Microarchitecture

D. Morano, A. Khalafi, D.R. Kaeli - Northeastern University, A.K. Uht - University of Rhode Island

 

Dissecting Cyclops: A Detailed Analysis of a Multithreaded Architecture

George Almasi, Calin Cascaval, Jos'e G. Castanos, Monty Denneau, Derek Lieber, Jose E. Moreira, Henry S. Warren Jr. - IBM Thomas J. Watson Research Center

 

On Cache Memory Hierarchy for Chip-Multiprocessor

Mohamed M. Zahran - University of Maryland

 

15:40 - 16:00 Break

 

16:00 - 17:40 Session II

 

An EGA Approach to the Compile-Time Assignment of Data to Multiple Memories in Digital-Signal Processors

Gary Gréwal, Thomas Wilson - University of Guelph, Andrew Morton - University of Waterloo

 

100 GOPS Vision Processor for Automotive Applications

Ulrich Ramacher, Nico Brüls, Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer - Infineon Technologies AG, Corporate Research

 

Indirect VLIW Memory Allocation for the ManArray Multiprocessor DSP

Nikos P. Pitsianis - Duke University, Gerald Pechanek - Lighting Hawk Consulting Inc.

 

A Linux Super Page Kernel for Alpha, Sparc64 and IA32: Reducing TLB Misses of Applications

Naohiko Shimizu and Ken Takatori - Tokai University

 

17:40 Concluding Remarks